1 of 8 083006 features 10-year minimum data retention in the absence of external power data is automatically protected during a power loss separate upper byte and lower byte chip- select inputs unlimited write cycles low-power cmos read and write access times as fast as 70ns lithium energy source is electrically disconnected to retain freshness until power is applied for the first time full 10% operating range (ds1258y) optional 5% operating range (ds1258ab) optional industrial temperature range of -40 c to +85 c, designated ind pin assignment pin description a0 to a16 - address inputs dq0 to dq15 - data in/data out ceu - chip enable upper byte cel - chip enable lower byte we - write enable oe - output enable v cc - power (+5v) gnd - ground description the ds1258 128k x 16 nonvolatile (nv) srams are 2,097,152-b it fully static, nv srams, organized as 131,072 words by 16 bits. each nv sram has a self -contained lithium energy source and control circuitry that constantly monitors v cc for an out-of-tolerance conditi on. when such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. dip-package ds1258 devices can be used in place of solutions that build nv 128k x 16 memory by utilizing a variety of discrete components. there is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. ds1258y/ab 128k x 16 nonvolatile sram www.maxim-ic.com 13 1 2 3 4 5 6 7 8 9 10 11 12 14 39 40-pin encapsulated package 740mil extended dq15 dq13 dq11 dq10 dq9 dq8 gnd dq7 dq5 dq6 v cc we a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 gnd a 8 a 6 a 7 40 38 37 36 35 34 33 32 31 30 29 27 28 cel dq14 dq12 ceu dq4 dq3 15 16 26 25 a 5 a 4 17 18 dq1 dq2 a 2 a 3 23 24 dq0 oe 19 20 22 21 a 1 a 0
ds1258y/ab 2 of 8 read mode the ds1258 devices execute a read cycle whenever we (write enable) is inactive (high) and either/both of ceu or cel (chip enables) are active (low) and oe (output enable) is active (low). the unique address specified by the 17 addr ess inputs (a0-a16) defines whic h of the 131,072 words of data is accessed. the status of ceu and cel determines whether all or part of the addresse d word is accessed. if ceu is active with cel inactive, then only the upper byte of the addressed word is accessed. if ceu is inactive with cel active, then only the lower byte of the addressed word is accessed. if both the ceu and cel inputs are active (low), then the entire 16-bit wo rd is accessed. valid data will be available to the 16 data output drivers within t acc (access time) after the last address input signal is stable, providing that ceu , cel and oe access times are also satisfied. if ceu , cel , and oe access times are not satisfied, then data access must be measured from the later occurring signal, and the limiting parameter is either t co for ceu , cel , or t oe for oe rather than address access. write mode the ds1258 devices execute a write cycle whenever we and either/both of ceu or cel are active (low) after address inputs are stable. th e unique address specified by the 17 address inputs (a 0-a16) defines which of the 131,072 words of data is accessed. the status of ceu and cel determines whether all or part of the addressed word is accessed. if ceu is active with cel inactive, then only the upper byte of the addressed word is accessed. if ceu is inactive with cel active, then only the lower byte of the addressed word is accessed. if both the ceu and cel inputs are active (low), then the entire 16-bit word is accessed. the write cycle is terminated by the earlier rising edge of ceu and/or cel , or we . all address inputs must be kept va lid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inactive (high) during write cycles to avoid bus c ontention. however, if the output drivers are enabled ( ceu and/or cel , and oe active) then we will disable the outputs in t odw from its falling edge. read/write function table 1 oe we cel ceu v cc current dq0-dq7 dq8-dq15 cycle performed h h x x i cco high-z high-z output disabled l h l l output output l h l h output high-z l h h l i cco high-z output read cycle x l l l input input x l l h input high-z x l h l i cco high-z input write cycle x x h h i ccs high-z high-z output disabled data retention mode the ds1258ab provides full functional capability for v cc greater than 4.75v, and write protects by 4.5v. the ds1258y provides full functional capability for v cc greater than 4.5v and write protects by 4.25v. data is maintained in the absence of v cc without any additional support circuitry. the nv static rams constantly monitor v cc . should the supply voltage decay, the nv srams automatically write protect themselves, all inputs become ?don?t care, ? and all outputs become high impedance. as v cc falls below approximately 3.0v, a power switching circuit connects the lithium energy source to ram to
ds1258y/ab 3 of 8 retain data. during power-up, when v cc rises above approxima tely 3.0v, the power switching circuit connects external v cc to ram and disconnects the lithium energy source. normal ram operation can resume after v cc exceeds 4.75v for the ds1258ab and 4.5v for the ds1258y. freshness seal the ds1258 devices are shipped from dallas se miconductor with the lithium energy sources disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than v tp , the lithium energy source is enabled for battery backup operation. absolute maximum ratings* voltage on any pin relative to ground -0.3v to +6.0v operating temperature range 0c to +70c, -40 c to +85 c for industrial parts storage temperature range -40c to +70c, -40 c to +85 c for industrial parts soldering temperature +260c for 10 seconds caution: do not reflow (wave or hand solder only) * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (t a : see note 10) parameter symbol min typ max units notes ds1258ab power supply voltage v cc 4.75 5.0 5.25 v ds1258y power supply voltage v cc 4.5 5.0 5.5 v logic 1 v ih 2.2 v cc v logic 0 v il 0.0 +0.8 v dc electrical (v cc = 5v 5% for ds1258ab) characteristics (t a : see note 10) (v cc = 5v 10% for ds1258y) parameter symbol min typ max units notes input leakage current i il -2.0 +2.0 a i/o leakage current ceu = cel v ih v cc i io -1.0 +1.0 a output current @ 2.4v i oh -1.0 ma output current @ 0.4v i ol 2.0 ma standby current ceu , cel =2.2v i ccs1 0.7 1.5 ma standby current ceu , cel =v cc - 0.5v i ccs2 150 300 a operating current i cco1 170 ma write protection voltage (ds1258ab) v tp 4.50 4.62 4.75 v write protection voltage (ds1258y) v tp 4.25 4.37 4.5 v
ds1258y/ab 4 of 8 capacitance (t a = +25 c) parameter symbol min typ max units notes input capacitance c in 20 25 pf input/output capacitance c i/o 5 10 pf ac electrical (v cc = 5v 5% for ds1258ab) characteristics (t a : see note 10) (v cc = 5v 10% for ds1258y) DS1258AB-70 ds1258y-70 ds1258ab-100 ds1258y-100 parameter symbol min max min max units notes read cycle time t rc 70 100 ns access time t acc 70 100 ns oe to output valid t oe 35 50 ns ceu or cel to output valid t co 70 100 ns oe or ceu or cel to output valid t coe 5 5 ns 5 output high z from deselection t od 25 35 ns 5 output hold from address change t oh 5 5 ns write cycle time t wc 70 100 ns write pulse width t wp 55 75 ns 3 address setup time t aw 0 0 ns write recovery time t wr1 t wr2 5 15 5 15 ns ns 12 13 output high z from we t odw 25 35 ns 5 output active from we t oew 5 5 ns 5 data setup time t ds 30 40 ns 4 data hold time t dh1 t dh2 0 10 0 10 ns ns 12 13 read cycle see note 1
ds1258y/ab 5 of 8 write cycle 1 see note 2, 3, 4, 6, 7, 8 and 12 write cycle 2
ds1258y/ab 6 of 8 power-down/power-up condition power-down/power-up timing (t a : see note 10) parameter symbol min typ max units notes ceu , cel at v ih before power-down t pd 0 s 11 v cc slew from v tp to 0v t f 300 s v cc slew from 0v to v tp t r 300 s ceu , cel at v ih after power-up t rec 2 125 ms (t a =+25 c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstance are negative undershoots, of an y amplitude, allowed when device is in battery backup mode. notes: 1) we is high for a read cycle. 2) oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high impedance state. 3) t wp is specified as the logical and of ceu or cel and we . t wp is measured from the latter of ceu , cel or we going low to the earlier of ceu , cel or we going high. 4) t ds is measured from the earlier of ceu or cel or we going high. 5) these parameters are sampled with a 5pf load and are not 100% tested. 6) if the ceu or cel low transition occurs simultaneously with or later than the we low transition in the output buffers remain in a high impedance state during this period. 7) if the ceu or cel high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in high imp edance state during this period.
ds1258y/ab 7 of 8 8) if we is low or the we low transition occurs prior to or simultaneously with the ceu or cel low transition, the output buffers remain in a high impedance state during this period. 9) each ds1258 has a built-in switch that disconnect s the lithium source until the user first applies v cc . the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is first applied by the user. this parameter is a ssured by component selec tion, process control, and design. it is not measured directly during production testing. 10) all ac and dc electrical characteristics are valid over the full operating temperature range. for commercial products, this range is 0 c to +70 c. for industrial products, this range is -40 c to +85 c. 11) in a power-down condition the voltage on any pin may not exceed the voltage on v cc . 12) t wr1 , t dh1 are measured from we going high. 13) t wr2 , t dh2 are measured from ceu or cel going high. 14) ds1258 dip modules are recognized by underwriters laboratory (u.l. ? ) under file e99151. dc test conditions ac test conditions outputs open output load: 100 pf + 1ttl gate cycle = 200ns input pulse levels: all voltages are referenced to ground 0.0v to 3.0v timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5ns ordering information part number temperature range supply tolerance pin/package speed grade DS1258AB-70 0c to +70c 5v 5% 40 / 740 emod 70ns DS1258AB-70# 0c to +70c 5v 5% 40 / 740 emod 70ns DS1258AB-70ind -40c to +85c 5v 5% 40 / 740 emod 70ns DS1258AB-70ind# -40c to +85c 5v 5% 40 / 740 emod 70ns ds1258ab-100 0c to +70c 5v 5% 40 / 740 emod 100ns ds1258ab-100# 0c to +70c 5v 5% 40 / 740 emod 100ns ds1258y-70 0c to +70c 5v 10% 40 / 740 emod 70ns ds1258y-70# 0c to +70c 5v 10% 40 / 740 emod 70ns ds1258y-70ind -40c to +85c 5v 10% 40 / 740 emod 70ns ds1258y-70ind# -40c to +85c 5v 10% 40 / 740 emod 70ns ds1258y-100 0c to +70c 5v 10% 40 / 740 emod 100ns ds1258y-100# 0c to +70c 5v 10% 40 / 740 emod 100ns # denotes rohs-compliant product. * ds9034pc or ds9034pci (powercap) required. must be ordered separately.
ds1258y/ab 8 of 8 ds1258y/ab nonvolatile sram 40-pin, 740-mil extended module pkg 40-pin dim min max a in. mm 2.080 52.83 2.100 53.34 b in. mm 0.715 18.16 0.740 18.80 c in. mm 0.345 8.76 0.365 9.27 d in. mm 0.085 2.16 0.115 2.92 e in. mm 0.015 0.38 0.030 0.76 f in. mm 0.120 3.05 0.160 4.06 g in. mm 0.090 2.29 0.110 2.79 h in. mm 0.590 14.99 0.630 16.00 j in. mm 0.008 0.20 0.012 0.30 k in. mm 0.015 0.43 0.025 0.58
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